Field of the Invention
The invention relates to an integrated semiconductor circuit, such as an A/D converter, including a first zone in which capacitors are disposed, the capacitors having capacitor plates being formed of a first conductive layer and a second conductive layer, and a second zone in which circuit elements are disposed. The invention also relates to a process for producing the circuit.
In many types of integrated semiconductor circuits, the problem of producing one or more capacitors with a very precisely defined capacitance plays a major role. The absolute value of the capacitance and/or the relative accuracy of the capacitance of the different capacitors can be essential.
One example thereof are A/D converters, which are typically made with the aid of capacitor networks. For that purpose, in 8-bit converters, for instance, the capacitors must have a relative accuracy of less than 200 ppm. That is necessary, since for unequivocal conversion of analog signals to digital signals or vice versa, there must be a monotonic relationship between the analog signal and the digital signal, or at least the non-monotony must be less than one hit (namely the least significant bit or LSB). The matching behavior of the circuit is determined, among other factors, by how well that requirement is met (see IEEE Transactions on Circuits and Systems, Vol. 25, No. 7, July 1978, p. 419).
In CMOS processes, for instance, suitable capacitances can be achieved in different planes, such as polysilicon to substrate, polysilicon 1 to metal 1, polysilicon 1 to polysilicon 2, or metal 1 to metal 2. In the polysilicon planes as capacitor plates, it must be taken into account that the dopings must be relatively high (approximately 1020/cm.sup.2), if the necessary constancy is to be achieved upon a voltage change. Such high dopings cannot always meet the requirements of the overall process in terms of the gate polysilicon, or they necessitate an additional doping with a mask in the silicon substrate. If polysilicon and substrate are used for the capacitance, then because of the usually slight gate oxide thicknesses of modern CMOS generations, high specific capacitances are attained, which is deleterious to the recharging time. However, given sufficiently low structural tolerances of lithography and etching processes, adequately small capacitor surface areas (to increase the speed) can be produced with the necessary accuracy. At least in process options that have two polysilicon planes, it may be advantageous, in terms of those peripheral conditions, to produce the capacitances using one or both polysilicon planes.
If only one polysilicon plane is processed, then often a metal 1/metal 2 capacitance is more suitable. It is also successfully used in 0.7 .mu.m CMOS generations, for 10-bit A/D converters with linearities of 0.5 LSB.
Particularly in future generations, the dielectric between the conductive layer, from which the capacitor plates are formed, must be planarized over a long range. For example, the typical planarizing lengths in the intermetal dielectric, when spin-on glass (SOG) planarizing techniques are employed, are from 10 to 100 .mu.m. Given the typical dimensions of an A/D converter capacitor network of a few hundred micrometers, this leads to unacceptable fluctuations in the thickness of the capacitor dielectric. In 10-bit A/D converters, the planarizing with SOG already leads to errors in linearity of from 2 to 4 LSB, and therefore to massive yield losses because of the occurrence of what are known as missing codes.